As network link speeds race to 10 Gigabit/sec and beyond, Internet servers will rely on programmable network interface cards (NICs) to relieve the ever increasing frame processing burdens. To meet that need, this work introduces a scalable, programmable NIC architecture that saturates a full-duplex 10 Gigabit/sec Ethernet link. This proposed architecture utilizes simple parallel processors instead of a single complex core to satisfy its frame-processing requirements, thereby reducing core power by 63%. To exploit lower-frequency parallel resources, this work also contributes an enhanced event queue firmware mechanism that enables frame-level parallelism.; Although simulation provides a detailed, inexpensive method to evaluate architectures and software, no detailed architectural simulator has previously targeted NIC designs. This work therefore contributes Spinach, a new simulation toolset that accurately models programmable NICs in microarchitectural detail. A Spinach model of an existing Gigabit NIC validates hardware benchmarks within 8.9% and yields solutions to previously undiscovered performance bottlenecks.
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