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An augmented phase-leg configuration (APLC) with shoot-through immunity for insulated gate power switches.

机译:具有直通抗扰性的增强相脚配置(APLC),用于绝缘栅电源开关。

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摘要

This thesis presents a new inverter phase-leg configuration that is inherently immune to shoot-through failures, eliminating one of the most serious failure modes in the conventional phase-leg configuration. The augmented phase-leg configuration (APLC) requires a single command signal and a simplified gate drive configuration to control the phase leg operation. The APLC also provides a significant advantage of eliminating the need for introducing dead-time intervals in the control of standard inverter phase legs. Very low levels of both harmonic distortion and nonlinearity are demonstrated using this new phase-leg configuration, making it attractive for many motor drive applications including low-frequency sensorless vector control, flux estimation, and open-loop voltage control. A combination of analysis, simulation, and experimental tests are presented to confirm the scalability of the APLC to current levels of 100A or higher. The importance of minimizing key parasitic inductances is investigated, and a set of physical layout design guidelines is presented to assist in the development of new APLC implementations. The net reduction of the phase-leg efficiency caused by the series diode is found to be small (1%) for bus voltages above 100Vdc. An alternative APLC topology is presented using a synchronous rectifier MOSFET that offers reduced losses by decreasing the forward conduction drop of the series diode. A self-boot charge pump for the high-side gate drive power supply is introduced to eliminate the necessity of transformers for an integrated power module design. This self-boost power supply configuration is compatible with the APLC and further enhances its robustness for operation over the complete range of PWM duty cycle values. The results of this thesis provide valuable techniques and tools for developing new integrated power electronic modules (IPEMs) that are highly integrated, intelligent, and robust.
机译:本文提出了一种新的逆变器相脚配置,该配置固有地不受直通故障的影响,从而消除了传统相脚配置中最严重的故障模式之一。增强的相脚配置(APLC)需要单个命令信号和简化的栅极驱​​动配置来控制相脚操作。 APLC还提供了一个显着的优势,即无需在标准逆变器相脚的控制中引入停滞时间间隔。利用这种新的相脚配置,谐波失真和非线性都非常低,这使其对许多电机驱动应用具有吸引力,包括低频无传感器矢量控制,磁通估计和开环电压控制。结合了分析,模拟和实验测试,以确认APLC到100A或更高电流水平的可扩展性。研究了最小化关键寄生电感的重要性,并提出了一组物理布局设计指南,以协助开发新的APLC实现。对于高于100Vdc的总线电压,由串联二极管引起的相脚效率的净降低幅度很小(<1%)。提出了使用同步整流MOSFET的另一种APLC拓扑,该拓扑通过减小串联二极管的正向导通压降来降低损耗。引入了用于高端栅极驱动电源的自启动电荷泵,以消除使用变压器进行集成电源模块设计的必要性。这种自升压电源配置与APLC兼容,并在整个PWM占空比值范围内进一步增强了其鲁棒性。本文的结果为开发高度集成,智能且强大的新型集成电力电子模块(IPEM)提供了有价值的技术和工具。

著录项

  • 作者

    Park, Shihong.;

  • 作者单位

    The University of Wisconsin - Madison.;

  • 授予单位 The University of Wisconsin - Madison.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2004
  • 页码 211 p.
  • 总页数 211
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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