This thesis presents the theory, the design and the implementation of the octave-band and full tree wavelet transforms on a VLSI chip using VHDL that will minimize the surface usage of the chip. This reduction is possible due to the use of the idle periods of the unit to carry out the calculations of the higher levels as well as the use of the method known under the name of Lifting scheme, which makes it possible to reduce the complexity of the implementation of the complementary filters by 50% compared with the more traditional implementation using convolution.; The design process must consider the number of computation units, the input/output data rate and the storage space. The storage space must be independent of the input data length, since this might be very large. These criteria will affect the total area as well as the power consumption and maximum clock speed of the realization.; Some additional requirements for the DWT implementations should be considered. The architecture should be able to perform a signal reconstruction with only minor modifications. It might also be important to reconfigure the realization for the use of different filter coefficients and lengths.; All details of this implementation, especially the different design units, will be described. The results of a final simulation using a set of sample data will be discussed in terms of the processor's complexity and achievable precision. The achieved improvements will be demonstrated by comparing the results to a conventional FIR filter implementation. Further, possible extensions to the project will be given.
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