As technology scales, billion transistor chips will become a reality in the near future. Reliable and efficient use of the available communication medium (on chip interconnects, buffers and routers) is of critical importance for such a chip. The focus of this work is on modeling a "Network on Chip" to analyze the performance. We model the on-chip network as a queuing network with blocking and analyze the network. Two possible architectures are considered, the enhanced packet-switched architecture and the packet-switched architecture. The architectures differ in the routing network; the routing networks are analyzed and modeled to estimate the performance. We also discuss the need for "Network on Chip" in the near future.
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