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ICP etching of silicon for micro and nanoscale devices.

机译:用于微米和纳米级设备的ICP硅蚀刻。

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摘要

The physical structuring of silicon is one of the cornerstones of modern microelectronics and integrated circuits. Typical structuring of silicon requires generating a plasma to chemically or physically etch silicon. Although many tools have been created to do this, the most finely honed tool is the Inductively Couple Plasma Reactive Ion Etcher. This tool has the ability to finesse structures from silicon unachievable on other machines. Extracting structures such as high aspect ratio silicon nanowires requires more than just this tool, however. It requires etch masks which can adequately protect the silicon without interacting with the etching plasma and highly tuned etch chemistry able to protect the silicon structures during the etching process.;In the work presented here, three highly tuned etches for silicon, and its oxide, will be described in detail. The etches presented utilize a type of etch chemistry which provides passivation while simultaneously etching, thus permitting silicon structures previously unattainable. To cover the range of applications, one etch is tuned for deep reactive ion etching of high aspect ratio micro-structures in silicon, while another is tuned for high aspect ratio nanoscale structures. The third etch described is tuned for creating structures in silicon dioxide. Following the description of these etches, two etch masks for silicon will be described. The first mask will detail a highly selective etch mask uniquely capable of protecting silicon for both etches described while being compatible with mainstream semiconductor fabrication facilities. This mask is aluminum oxide. The second mask detailed permits for a completely dry lithography on the micro and nanoscale, FIB implanted Ga etch masks. The third chapter will describe the fabrication and in situ electrical testing of silicon nanowires and nanopillars created using the methods previously described. A unique method for contacting these nanowires is also described which has enabled investigation into the world of nanoelectronics. The fourth and final chapter will detail the design and construction of high magnetic fields and integrated planar microcoils, work which was enabled by the etching detailed here. This research was directed towards creation of a portable NMR machine.
机译:硅的物理结构是现代微电子学和集成电路的基石之一。硅的典型结构化需要产生等离子体以化学或物理地蚀刻硅。尽管已经创建了许多工具来执行此操作,但最精细的工具是感应耦合等离子体反应离子刻蚀机。该工具能够从其他机器上无法实现的硅中细化结构。但是,提取诸如高长宽比的硅纳米线之类的结构不仅需要此工具,还需要更多。它需要能够在不与蚀刻等离子体相互作用的情况下充分保护硅的蚀刻掩模,以及能够在蚀刻过程中保护硅结构的高度调整的蚀刻化学物质。在本文介绍的工作中,对硅及其氧化物进行了三种高度调整的蚀刻,将详细描述。所提出的蚀刻利用一种蚀刻化学类型,其在进行蚀刻的同时提供钝化,因此允许先前无法获得的硅结构。为了涵盖应用范围,调整了一种蚀刻以对硅中高深宽比的微结构进行深反应离子刻蚀,而另一种调整为高深宽比的纳米级结构。调整所述的第三蚀刻以在二氧化硅中产生结构。在这些蚀刻的描述之后,将描述两个用于硅的蚀刻掩模。第一掩模将详细描述高度选择性的蚀刻掩模,该掩模能够唯一地保护所述两种蚀刻的硅,同时与主流的半导体制造设备兼容。该掩模是氧化铝。详细介绍的第二个掩模允许在微米和纳米级FIB注入Ga蚀刻掩模上进行完全干法光刻。第三章将描述使用上述方法创建的硅纳米线和纳米柱的制造和原位电测试。还描述了一种用于接触这些纳米线的独特方法,这使人们能够研究纳米电子领域。第四章也是最后一章将详细介绍高磁场和集成平面微线圈的设计和构造,这些工作是通过此处详述的蚀刻实现的。这项研究的目的是创建便携式核磁共振仪。

著录项

  • 作者

    Henry, Michael David.;

  • 作者单位

    California Institute of Technology.;

  • 授予单位 California Institute of Technology.;
  • 学科 Physics Electricity and Magnetism.;Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2010
  • 页码 219 p.
  • 总页数 219
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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