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A CMOS Sigma-Delta Digital Intermediate Frequency to Radio Frequency Transmitter.

机译:CMOS Sigma-Delta数字中频到射频发射机。

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摘要

During the last decades the development of the transistor and its continuous down-scaling allowed the appearance of cost effective wireless communication systems. New generation wideband wireless mobile systems demand high linearity, low power consumption and the low cost devices. Traditional RF systems are mainly analog-based circuitry. Contrary to digital circuits, the technology scaling results in reduction on the maximum voltage swing which makes RF design very challenging. Pushing the interface between the digital and analog boundary of the RF systems closer to the antenna becomes an attractive trend for modern RF devices. In order to take full advantages of the deep submicron CMOS technologies and digital signal processing (DSP), there is a strong trend towards the development of digital transmitter where the RF up-conversion is part of the digital-to-analog conversion (DAC). This thesis presents a new digital intermediate frequency (IF) to RF transmitter for 2GHz wideband code division multiple access (W-CDMA). The proposed transmitter integrates a 3-level digital IF current-steering cell, an up-conversion mixer with a tuned load and an RF variable gain amplifier (RF VGA) with an embedded finite impulse response (FIR) reconstruction filter in the up-conversion path. A 4th-order 1.5-bit IF bandpass sigma delta modulator (BP SigmaDeltaM) is designed to support in-band SNR while the out-of-band quantization noise due to the noise shaping is suppressed by the embedded reconstruction filter to meet spectrum emission mask and ACPR requirements. The RF VGA provides 50dB power scaling in 10-dB steps with less than 1dB gain error. The design is fabricated in a 0.18microm CMOS technology with a total core area of 0.8 x 1.6 mm2. The IC delivers 0dBm output power at 2GHz and it draws approximately 120mA from a 1.8V DC supply at the maximum output power. The measurement results proved that a digital-intensive digital IF to RF converter architecture can be successfully employed for W-CDMA transmitter application.
机译:在过去的几十年中,晶体管的发展及其不断缩小的规模使得出现了具有成本效益的无线通信系统。新一代宽带无线移动系统需要高线性度,低功耗和低成本的设备。传统的射频系统主要是基于模拟的电路。与数字电路相反,该技术的扩展可降低最大电压摆幅,这使RF设计非常具有挑战性。将RF系统的数字和模拟边界之间的接口推向更靠近天线的位置,已成为现代RF设备的诱人趋势。为了充分利用深亚微米CMOS技术和数字信号处理(DSP)的优势,数字发射机的发展趋势非常明显,其中射频上变频是数模转换(DAC)的一部分。本文提出了一种用于2GHz宽带码分多址(W-CDMA)的RF发送器数字中频(IF)。拟议的发射器集成了一个3级数字IF电流控制单元,一个带调谐负载的上变频混频器以及一个在上变频中带有嵌入式有限脉冲响应(FIR)重构滤波器的RF可变增益放大器(RF VGA)路径。设计了一个四阶1.5位IF带通Σ-Δ调制器(BP SigmaDeltaM)以支持带内SNR,同时由于噪声整形而导致的带外量化噪声被嵌入式重建滤波器抑制,以满足频谱发射掩模的要求。和ACPR要求。 RF VGA以10dB的步长提供50dB的功率缩放,增益误差小于1dB。该设计采用0.18微米CMOS技术制造,总核心面积为0.8 x 1.6 mm2。该IC在2GHz时提供0dBm的输出功率,并且以最大输出功率从1.8V直流电源汲取约120mA的电流。测量结果证明,数字密集型数字IF到RF转换器架构可成功用于W-CDMA发射机应用。

著录项

  • 作者

    Han, Yongping.;

  • 作者单位

    Arizona State University.;

  • 授予单位 Arizona State University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2012
  • 页码 110 p.
  • 总页数 110
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

  • 入库时间 2022-08-17 11:42:26

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