Exploration of Graphene for Tunnel Devices and Electrodes in Next-Generation Green Electronics.

摘要

With the rapid scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs), the passive power dissipation is becoming comparable to the active power consumption. The passive power dissipation can be reduced by increasing the threshold voltage in MOSFETs at the expense of lower drive current and higher delay. An effective way to lower the passive power is to reduce the subthreshold swing (S), which is the amount of gate voltage required to change the device current by an order of magnitude in the subthreshold region. In this dissertation, novel applications of graphene in low-power and energy-efficient electronics are investigated. To that purpose, first the design of heterostructure tunnel FET (TFET) based on conventional materials including silicon and germanium is investigated. It is shown that while TFETs can exhibit S values much lower than the MOSFET's fundamental limit of 60 mV/dec, the ON currents of TFETs based on these materials remain well below that of MOSFETs. Then, the design of TFET based on graphene nanoribbons (GNRs) is investigated. The graphene nanoribbons offer several key advantages over conventional materials. These advantages include the tunable bandgap, the superb gate electrostatic control due to the atomically thin structure, the pristine surface, which reduces the trap density, the high carrier mobility, high thermal stability and high mechanical flexibility. Homojunction and heterojunction TFETs based on GNRs are proposed and their characteristics are investigated using the Non-Equilibrium Green's Function (NEGF) formalism. The GNR based TFETs are shown to exhibit very high ON currents as well as S values down to 15 mV/dec. In addition, alternative devices and circuits based on GNRs are proposed and studied in this dissertation that can lead to ultra low-power consumption. A novel negative differential resistance (NDR) device (in the form of an Esaki Tunnel diode) based on GNR is proposed, which can be used in the design of ultra-compact memory cells. The proposed NDR devices exhibit high peak-to-valley current ratio of ~1E5 as well as high drive current of ~700muA/mum. The proposed device offers high flexibility in terms of the design and optimization, and is suitable for digital logic applications. A complementary logic is developed based on the proposed device, which can be operated down to 200 mV of supply voltage. The complementary logic is used in design of an ultra-compact bi-stable switching static memory cell. Due to its compactness and high drive current, the proposed memory cell can outperform the conventional static random access memory cells in terms of switching speed and power consumption. Finally, some key properties of graphene relevant to devices and interconnects in integrated circuits as well as to transparent electrodes in a variety of applications, such as contact resistance, trap state density and optical transparency are investigated. The contact resistance of metal to multi-layer graphene (MLG) structures has been investigated thoroughly by developing a rigorous 1D model. The model captures the effect of both the top-contact and edge-contact to graphene. It is shown that the edge-contacts reduce the total resistance of the metal-MLG structure by up to 2 orders of magnitude. Moreover, a self-consistent model is developed to capture the electrostatics of few-layer graphene (FLG) on semiconductors. The FLG is a promising material as a transparent electrode in various applications such as solar cells, touch panels, display light sensors and light emitting devices. The model predicts that the Schottky barrier height of the FLG/Semiconductor interfaces can be engineered to sub-200 mV. Furthermore, the charge density of FLG can be improved by a few orders of magnitude to improve its electrical conductivity. Lastly the role of trap states at the graphene/oxide interface on the current saturation of graphene FETs (GFETs) is investigated experimentally. Through carefully fabricated GFETs and systematically designed experiments, the physical nature of current saturation in GFETs is revealed for the first time. It is shown for the first time that the trap states in the oxide and at the graphene/oxide interface play crucial role in determining the nature of current saturation in GFETs. These trap states are shown to get charged or discharged depending on the bias conditions, and lead to the appearance or disappearance of current saturation in GFETs. The consideration of the effects of trap-states is shown to be necessary for accurate characterization, modeling and parameter extraction of GFETs.