An FPGA-based singular value decomposition processor.

摘要

This thesis presents a FPGA-based Singular Value Decomposition processor which uses the two-sided rotation Jacobi SVD algorithm. A mesh-connected array structure based on Brent, Luk, and Van Loan is proposed to shorten the iteration of the computation and improve the implementation speed of the processor. The proposed array consists of a n2xn 2 array of 2 x 2 processor elements to compute the SVD of an n x n matrix. The trigonometric functions and the vector multiplication in the algorithm are tailored to use the CORDIC (COordinate Rotation Digital Computer) algorithms for hardware-efficient solutions.;Two SVD processors, the Basic SVD Processor and the Extended SVD Processors, are developed in this thesis. In the Basic SVD Processor, the maximum matrix which can be accommodated in the targeted device is explored by taking advantage of the features of the device, and several design techniques are used to speed the SVD computation. The goal of the Extended SVD Processor is to compute a big SVD without increasing the processor size by reusing the SVD array of the Basic SVD Processor. Both of the SVD processors can successfully compute the SVD, and the errors from the hardware simulation results are quantified to evaluate the SVD processor in the thesis.