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Sensitivity analysis on impact of hardware resources in SMT processors.

机译:对SMT处理器中硬件资源的影响的敏感性分析。

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摘要

The microprocessor performance is increased by allowing multiple threads per clock cycle to issue instructions in Simultaneous multithreading processors. Branch prediction and shared hardware resources are the key components of processor performance. Some of the techniques affect the performance in SMT Processors even if the shared hardware resources are high. Evaluating the effect of parameters like cache, physical register sizes, Issue Queue, Instruction fetch policies and branch prediction accuracy on the performance improvement in the SMT processors demonstrates the efficacy of hardware resources among the threads.;This research is oriented towards the analysis on the current fetch policies and hardware resources in SMT processors. The optimization of overall throughput and or fairness depends on how the running threads are executed and the resource utilization among the running threads. The performance of a processor is based on the fetch policy used and the workloads executed among the threads.
机译:通过允许每个时钟周期有多个线程在同步多线程处理器中发出指令,可以提高微处理器的性能。分支预测和共享硬件资源是处理器性能的关键组成部分。即使共享的硬件资源很高,某些技术也会影响SMT处理器的性能。评估缓存,物理寄存器大小,发出队列,指令提取策略和分支预测精度等参数对SMT处理器性能提高的影响,证明了线程之间硬件资源的功效。 SMT处理器中的当前获取策略和硬件资源。总体吞吐量和/或公平性的优化取决于运行线程的执行方式以及运行线程之间的资源利用率。处理器的性能基于所使用的获取策略和线程之间执行的工作负载。

著录项

  • 作者

    Davanam, Naveen.;

  • 作者单位

    The University of Texas at San Antonio.;

  • 授予单位 The University of Texas at San Antonio.;
  • 学科 Engineering Computer.
  • 学位 M.S.
  • 年度 2010
  • 页码 55 p.
  • 总页数 55
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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