Design techniques for high performance CMOS flash analog-to-digital converters.

摘要

This thesis describes research on very-high-sampling-rate, moderate-resolution, CMOS, analog-to-digital converters (ADCs). The sampling rate of an ADC can be extended through the use of a faster process technology (e.g., GaAs), or through time-interleaving. However, circuit techniques that extend the sampling rates of an ADC for a given CMOS technology, are still fundamentally required. Flash ADCs generally achieve the highest sampling rate. Architectures and building blocks of flash ADCs are investigated.; The comparator is one of the most critical components in a flash ADC. New circuit techniques that improve comparator performance are proposed. The addition of on-chip, compact, low Q inductors improves the sampling speed of the comparators without an increase in power consumption. Compact inductors consume 1% of the die area required for conventional on-chip inductors. The value of inductance is optimized through the consideration of both tracking and regenerative time constants. A clocked-cascode structure in the preamplifier reduces kickback to the reference. The use of a reduced swing sampling clock further extends sampling rate.; The use of minimum length transistors also helps to extend sampling speed and improve power efficiency. Offset correction is required even for moderate resolutions, because of the significant mismatch of minimum length transistors in deep-submicron CMOS. Comparator redundancy, DAC trimming at the comparator output, and DAC trimming at the reference input are proposed to calibrate comparator offset. Offset correction and calibration are optimized to maximize ADC yield and to minimize DNL and INL errors.; Two non-interleaved prototype flash ADCs were designed, fabricated and tested. A 4 bit ADC was implemented in 0.18 mum TSMC CMOS and a 5 bit ADC was implemented in 90 nm Intel CMOS. The 4 bit ADC achieves a sampling rate of up to 4 GHz with a measured effective resolution of 3.89 bits. The ADC consumes 551 mW at 3 GS/s with a 1.5 GHz full power input, and of this, the analog portion consumes 78 mW. The 5 bit ADC also achieves a sampling rate of up to 4 GHz and an effective resolution of 4.28 effective bits. This ADC consumes 227 mW at 3.5 GS/s with 1 GHz full power input. The analog circuitry of the 5 bit ADC consumes 115 mW. Both these ADCs achieve over twice the sampling rate of recently published state-of-the-art, non-interleaved, low-resolution CMQS ADCs. (Abstract shortened by UMI.)