Deep-submicron CMOS design of high-performance low-power flash/folding analog-to-digital converters

摘要

High speed embedded ADC designs are a fundamental component of mobile applications. However, low-power and low-voltage constraints, as well as fast conversion rates are required for these systems, particularly for battery-powered devices. To meet these requirements, folding and interpolating ADC are widely used in embedded ADC for communications IC. This paper presents the design procedure of a 6-bit folding and interpolating analog-to-digital converter (ADC) operating at a conversion rate of 1 Gsamples/s while only dissipating 8 mW. Design challenges and potential solutions are presented and verified through an implementation of this ADC in 1.8 V 0.18 /spl mu/m standard CMOS technology.