A study of process variations and their impact analysis in RF circuits.

摘要

This thesis presents an in-depth empirical research to understand the impact of process variations in RF Circuits. We present a hierarchical two phase approach to study the impact of process based variations on device characteristics and circuit-level performance as well. The simulations based on Monte-Carlo techniques have been conducted extensively at different levels to gauge the impact of process variations. Such sensitivity analysis helps to identify the critical components for various RF Cores at both layout/fabrication level, as well as circuit-level, which affect the performance of the system in the face of process based variations. This knowledge helps designers make necessary changes in the design phase to improve yield at the production stage. Thus, the hierarchical defect mapping based on device/component performance and sensitivity helps in optimizing circuit design by suitable consideration of component topologies for robust design. From a testing perspective, the defect analysis can help identify realistic faults which are bound to occur in RF Circuits. This helps to reduce the test signal generation effort to detect different types of faults in these circuits, which in turn results in cost savings in the testing process. This work also focuses on exploratory investigations to find alternative techniques to Monte-Carlo simulation based approach. Further, new ideas based on extending fault equivalence concepts between catastrophic and parametric faults for ease of test generation in RF Circuits have also been presented. (Abstract shortened by UMI.)