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Designing high-performance microprocessors in 3-dimensional integration technology.

机译:设计采用3维集成技术的高性能微处理器。

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摘要

In this dissertation, we demonstrate the impact of a new emerging technology called 3D-integration technology on microprocessors. 3D-integration technology stacks transistors in the vertical dimension in addition to the conventional horizontal plane. The additional degree of connectivity in the vertical dimension enables circuit designers to replace global wires with short vertical interconnects, thus reducing delay, power consumption, and area. To adapt planar microarchitectures to 3D-integrated designs, we study several building blocks that together comprise a substantial portion of a processor's total transistor count. In particular, we focus our attention on three basic circuit classes: static random access memory circuits, associative logic circuits, and data processing circuits. We propose different 3D-integrated circuit designs to deal with the constraints of the conventional planar technology. Based on the 3D-integrated circuits, we propose high-performance 3D-integrated microprocessors and evaluate the impact on performance, power, and temperature. We demonstrate two different approaches to improve performance: clock speed improvement and IPC improvement. We demonstrate the simultaneous benefits of the 3D-integration and highlight the power density issue related to the 3D-integration technology. Next, we propose novel microarchitectural techniques to address the challenge of power density. We demonstrate that microarchitecture-level techniques can effectively control the power density in the 3D-integrated processors. The 3D-integrated processors provide a significant performance benefit over the planar processors while simultaneously reducing the total power. One of the key contributions of this dissertation is the temperature analysis that shows that the worst-case temperatures on the 3D-integrated processors can be effectively controlled using microarchitecture level techniques. The 3D-integration technology may extend the applicability of Moore's law for a few more technology generations.
机译:在本文中,我们演示了一种称为3D集成技术的新兴技术对微处理器的影响。 3D集成技术除了传统的水平面外,还以垂直方向堆叠晶体管。垂直维度上的附加连通度使电路设计人员可以用短的垂直互连代替全局导线,从而减少延迟,功耗和面积。为了使平面微体系结构适应3D集成设计,我们研究了几个构建块,这些构建块一起构成了处理器总晶体管数量的很大一部分。特别是,我们将注意力集中在三种基本电路类别上:静态随机存取存储器电路,关联逻辑电路和数据处理电路。我们提出了不同的3D集成电路设计来应对常规平面技术的限制。基于3D集成电路,我们提出了高性能3D集成微处理器,并评估了对性能,功率和温度的影响。我们演示了两种提高性能的方法:时钟速度改进和IPC改进。我们演示了3D集成的同时带来的好处,并重点介绍了与3D集成技术相关的功率密度问题。接下来,我们提出了新颖的微体系结构技术来应对功率密度的挑战。我们证明了微体系结构级别的技术可以有效地控制3D集成处理器中的功率密度。集成3D的处理器比平面处理器具有明显的性能优势,同时降低了总功耗。论文的主要贡献之一是温度分析,表明使用微体系结构级技术可以有效控制3D集成处理器的最坏情况温度。 3D集成技术可以将摩尔定律的适用性扩展到更多几代技术。

著录项

  • 作者

    Puttaswamy, Kiran.;

  • 作者单位

    Georgia Institute of Technology.;

  • 授予单位 Georgia Institute of Technology.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2007
  • 页码 172 p.
  • 总页数 172
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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