FPGA implementation of a MIMO system with RAKE receiver.

摘要

Multiple-Input Multiple-Output (MIMO) technology and Space Time Coding (STC) are the main focus in today's wireless communication systems (WCS) effort to improve bandwidth efficiency and reliability. Many research have been done on many STC and MIMO systems; most of them were done by software simulation. Field Programmable Gate Array (FPGA) based fast prototyping research, or hardware simulation of MIMO systems, is a step further to explore these technologies. It costs much less simulation time, it is closer to real world communication systems in terms of hardware and it can be used to simulate a more detailed part of a system, and predicts the problem, which cannot be found in software simulation. Most of FPGA implementation of MIMO systems deployed VHDL as an entry tool but did not investigate the Bit Error Rate (BER) performance of the implemented system due to the limitation of the developing tool. In this thesis, Alamouti's algorithm is implemented in Altera's FPGA developing kit, Stratix 1P1S80. In this implementation, MatLab/Simulink environment with Altera's blockset, DSP Builder, is used as entry tools. A soft logic analyzer of Altera called Signal Tap II is used for debugging. Hardware in the loop (HIL) is deployed for debugging and evaluating the BER performance as a function of the signal to noise ratio (SNR) for different channel scenarios. Lastly, a MIMO-CDMA system with RAKE receiver is designed and implemented.