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On generation of high quality tests for defect detection and diagnosis.

机译:用于缺陷检测和诊断的高质量测试的生成。

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摘要

Defect detection and defect diagnosis are two fundamental goals in VLSI testing. In this thesis, we present methods to generate tests of high quality for defect detection and defect diagnosis, and to order test patterns for higher diagnosis resolution when the fail data is truncated.; Defects in deep sub-micron VLSI circuits are known to be predominantly opens and bridges. We propose a uniform test generation method to model interconnect opens and bridges using constrained multiple line stuck-at fault model. A novel feature of the proposed fault model is its flexibility to accommodate increasing levels of accuracy. Additionally the model does not require accurate device level circuit models to achieve desired accuracy.; Redundant logic identification and removal are useful for logic optimization and testability enhancement. Based on our work in the modeling of multiple line stuck-at faults, we present new procedures for identifying redundant stuck-at faults including redundant multiple line stuck-at faults on the branches of fan-out stems. The methods proposed include new procedures to identify stuck-at faults that are simultaneously redundant thus allowing simultaneous removal of logic associated with several redundant faults.; Defect diagnosis plays a crucial role in silicon debug, field return analysis, yield learning and process improvement. We investigate the use of n-distinguishing test sets, which distinguish pairs of single stuck-at faults n times, to enhance the probability of distinguishing unmodeled defects. Independent of the specifics of the diagnosis procedure used, n-distinguishing test sets intrinsically offer enhanced defect diagnosis resolution. In addition, it is necessary for defect diagnosis to consider the situations where the fail data available to the diagnosis tool is truncated. We propose a test pattern ordering algorithm for defect diagnosis with truncated fail data. Higher diagnosis resolution can be achieved with the test set appropriately ordered using the proposed algorithm.
机译:缺陷检测和缺陷诊断是VLSI测试的两个基本目标。在本文中,我们提出了生成高质量测试以进行缺陷检测和缺陷诊断的方法,以及在故障数据被截断时订购测试模式以提高诊断分辨率的方法。众所周知,深亚微米VLSI电路中的缺陷主要是断路和桥接。我们提出一种统一的测试生成方法,以使用受约束的多线卡死故障模型对互连的开路和桥进行建模。提出的故障模型的一个新颖特征是其灵活性,可以适应不断提高的准确性。另外,该模型不需要精确的器件级电路模型即可达到所需的精度。冗余逻辑识别和删除对于逻辑优化和可测试性增强很有用。基于我们在多线路卡死故障建模方面的工作,我们提出了用于识别冗余卡死故障的新过程,包括在扇出杆的分支上冗余的多线路卡死故障。所提出的方法包括新的程序,以识别同时冗余的卡住故障,从而允许同时消除与若干冗余故障相关的逻辑。缺陷诊断在芯片调试,现场返回分析,良率学习和工艺改进中起着至关重要的作用。我们研究使用n区分测试集,该测试集将n对单个卡住的故障对进行了n次区分,以提高区分未建模缺陷的可能性。独立于所用诊断程序的细节,n区分测试集本质上可提供增强的缺陷诊断分辨率。此外,对于缺陷诊断,有必要考虑将诊断工具可用的故障数据截断的情况。我们提出了一种测试模式排序算法,用于通过截断故障数据进行缺陷诊断。使用建议的算法对测试集进行适当排序,可以实现更高的诊断分辨率。

著录项

  • 作者

    Chen, Gang.;

  • 作者单位

    The University of Iowa.;

  • 授予单位 The University of Iowa.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2006
  • 页码 113 p.
  • 总页数 113
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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