Co-design Methodology for SOC applications

摘要

This paper presents a co-design approach to implement system on chip (SoC). A development of embedded environment for attaining the high performance is achieved by implementing certain computational core in hardware and efficiently used by Software. The co-design methodology partitions the system into hardware and software parts using a cost function. The hardware core is simulated using VerilogXL and prototyped in VLSI using Synopsys and Cadence, while the software part is implemented using C++. The performance studies show that the average response time using the proposed co-design is 70 times faster than an all-software solution. The proposed co-design approach gains such impressive throughput improvement without sacrificing any flexibility.