A clock skew-compensation and/or duty-cycle correction circuit (CSADC) is indispensably required to maximize the performance of synchronous double edge triggered systems. Most conventional CSADCs adopted a cascade structure that inherits a lower performance property so as to slower the locking procedure, meanwhile the dual loop design results in more power consumption and design complexity. A range extending delay-recycled CSADC is proposed in this work. Compared to conventional CSADCs, the proposed circuit achieves at least a 2 times extension in bandwidth ratio, a 2.81 times reduction in power, and a 12 times reduction in power-to-bandwidth ratio.
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