A reconfigurable architecture for entropy decoding and IDCT in H.264

摘要

Reconfigurable hardware is an effective design option to cope with the increasing demands of simultaneous flexibility and computation power in system design. This paper explores techniques to combine the two entropy decoding methods, context-based adaptive binary arithmetic coding (CABAC) and context-based adaptive variable length coding (CAVLC), defined in the H.264 standard using the coarse-grain reconfigurable architecture. Coarsegrain reconfigurable architectures can provide obvious advantages over their fine-grain counterparts for some specific applications. By analyzing the similarities and differences between these two decoding processes, we show how to effectively merge CAVLC into a CABAC decoder. Experimental results reveal that about 1.5K savings in gate counts can be obtained using the proposed reconfigurable cell (RC) architecture, which corresponds to 25.4% area savings in implementing the CAVLC decoder. Moreover, using the idle time in RC arrays, the base cell can be extended to carry out the inverse discrete cosine transform with very limited overhead. Our entropy decoder design, operated in 66 MHz, can decode video sequences at MP@ Level 3.0 under the real-time constraint.