A 6-bit 1GS/s low-power flash ADC

摘要

This paper proposes a low-power design guideline for high speed ADCs, and a low-power ADC with this design guideline is fabricated in a 0.13 mum CMOS process. The experimental results show that the effective number of bit (ENOB) is 5.16 at the sampling frequency of 1 GHz, and the resolution bandwidth (ERBW) is higher than 500 MHz at 700 MS/s. Due to the high input bandwidth and low power consumption, this ADC is very suitable for UWB systems.