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9.1 A Low-Power Rail-to-Rail 6-bit Flash ADC Based on a Novel Complementary Average-Value Approach

机译：9.1基于新型互补平均值方法的低功耗轨到轨6位闪存ADC

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Hui-chin Tseng; Hsin-hung Ou; Chi-sheng Lin;
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年度 2013
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1. A novel online offset-cancellation mechanism in a low-power 6-bit 2GS/s flash-ADC [J] . Amini Abdollah, Baradaranrezaeii Ali, Hassanzadazar Mina Analog Integrated Circuits and Signal Processing . 2019,第2期

机译：低功耗6位2GS / S闪存 - ADC中的新型在线偏移消除机制
2. A low-power 6-bit MOS CML flash ADC with a novel multi-segment encoder for UWB applications [J] . Damghanian Masumeh, Azhari Seyed Javad Integration . 2017,第mara期

机译：具有用于UWB应用的新型多段编码器的低功耗6位MOS CML闪存ADC
3. A LOW-POWER LOW-VOLTAGE 6-BIT 1.33 GS/s FULLY MCML ALL NMOS FLASH ADC WITHOUT A FRONT-END T/H [J] . SARA NESHANI, SEYED JAVAD AZHARI Journal of circuits, systems and computers . 2013,第8期

机译：低功耗低电压6位1.33 GS / s完全MCML无前端T / H的全NMOS闪存ADC
4. A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach [C] . Hui-Chin Tseng, Hsin-Hung Ou . 2004

机译：基于新型互补均值方法的低功耗轨到轨6位闪存ADC
5. Time-Based, Low-Power, Low-Offset 5-Bit 1 Gs/S Flash ADC Design in 65nm CMOS Technology [D] . Nasrollahpour, Mehdi 2017

机译：采用65nm CMOS技术的基于时间的低功耗，低失调5位1 Gs / S闪存ADC设计
6. An RSSI-Based Low-Power Vehicle-Approach Detection Technique to Alert a Pedestrian [O] . Yoshito Watanabe, Yozo Shoji 2020

机译：基于RSSI的低功率车辆进近检测技术可提醒行人
7. Low-power 6-bit flash ADC for high-speed data converters architectures [O] . V. Ferragina, N. Ghittori, F. Maloberti -1

机译：低功耗6位闪存aDC，适用于高速数据转换器架构

9.1 A Low-Power Rail-to-Rail 6-bit Flash ADC Based on a Novel Complementary Average-Value Approach

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