A continuous-time delta-sigma modulator using feedback resistors

摘要

A third-order continuous-time delta-sigma comprised of Active-RC integrator and Gm-C integrator is presented. For the consideration of power, linearity and performance, the first integrator uses active-RC OpAmp and the others use Gm-C. To reduce the clock jitter sensitivity, we choose nonreturn-to-zero (NRZ) pulse shaping as our DAC type. For the realization of NTF zero optimization, we use resistors to reduce power consumption. The delta-sigma modulator is implemented in standard digital 0.18-mum CMOS process which achieves a 60-dB SNDR or 10-bits ENOB over a 1-MHz signal bandwidth at an OSR of 50. The power consumption of the continuous-time delta-sigma modulator itself is 13.7 mW from the 1.8-V supply.