A Low Cost Low Power Quaternary LUT Cell for Fault Tolerant Applications in Future Technologies

摘要

Field programmable gate arrays offer flexibility to program hardware systems together with the possibility to explore any level of parallelism available in the application. Unfortunately, this flexibility costs a huge amount of circuit area necessary to implement all the routing switches and wires. Also, device scaling in new and future technologies brings along a severe increase in the soft error rate of circuits, for combinational and sequential logic. In order to reduce the impact of the wires and switches and cope with SETs in FPGAs, this work proposes a low power voltage-mode quaternary LUT (QLUT) design that uses quaternary logic to reduce the area spent in switches and routing wires. At the same time, the proposed QLUT provides robustness against SETs. Results show that the fault tolerant QLUT here proposed detects all faults that can cause an error with significant less area and less power when comparing to the binary correspondent LUT protected with the DWC technique. In order to evaluate how the proposed QLUT will deal with the process variability of sub 90 nm technologies, extensive Monte Carlo simulations were performed and these results are here discussed.