The authors present an algorithmic derivation of logic systems fornsolving path delay test problems. In these logic systems, the state of ansignal represents any possible situation that can occur during twonconsecutive vectors. Starting from a set of valid input states, a statentransition graph is constructed to enumerate all possible statesnproduced by Boolean gates. Specifics of the test problem are used forndistinguishability criteria and to minimize the number of states. Forntest generation in combinational or sequential circuits, the authors usenthe algorithm to obtain optimal logic systems. They define optimality asnto the smallest number of logic states that provide the least possiblenambiguity. The ten-value logic of Fuchs et al. is found to be optimalnfor generating tests for single path delay faults but gives ambiguousnresults for multiple path activation. A new 23-value logic is derived asnan optimal system for solving the multiple path problem as well as thendelay test generation problem of sequential circuits. The limitationsnand capabilities of various logic systems are illustrated
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