JOGM: A CMOS cell layout style using jogged transistor gates

摘要

A new width minimizing layout style called jogged gate matrixn(JOGM) for CMOS cells is described. The traditional gate matrix layoutnstyle is modified by inserting 45° jogs into transistor gates. Thus,nJOGM improves CMOS cell width by 23% to 31% in comparison to traditionalngate matrix layout. An approach for automatic layout generation isnsuggested