High-level modeling using extended timing diagrams - A formalismfor the behavioral specification of digital hardware

摘要

The principles of high level modeling of digital hardware circuitsnusing the extended timing diagrams (ETD) formalism, which addsnconditions, events, action expressions, and particular constraints tontraditional timing diagrams, are described. Hierarchy and concurrencynare also integrated so that a full top-down design becomes possible,nenhancing at the same time the readability. While, for simulationnpurposes, the implementation of the formalism generates behavioral VHDLn(VHSIC Hardware Description Language) models, a dedicated high-levelntranslator generates VHDL code for synthesis. Both the ETD formalism andnits implementation are part of MODES, a more complex modeling expertnsystem including complementary editors