首页>
外国专利>
Using patterns for high-level modeling and specification of properties for hardware systems
Using patterns for high-level modeling and specification of properties for hardware systems
展开▼
机译:使用模式进行硬件系统的高级建模和属性规范
展开▼
页面导航
摘要
著录项
相似文献
摘要
This invention is a high-level language to specify electronic system design patterns for functional verification. This invention includes automatic translation of the high-level language specification into assertion code from these patterns and temporal properties for design verification. This eliminates the need to code extra RTL to handle features such as pipelines and bus priorities. Such common features are specified only in high-level patterns and temporal properties to be verified. This is advantageous because less verification code to be written, automated synthesis of assertions enforces monitor-style of writing assertions rather than generator-style, and the high-level code can be seamlessly migrated to another verification tool by producing another code generator for the new assertion language.
展开▼