A method for diagnosing implementation errors in synchronoussequential circuits and its implications on synthesis

摘要

The authors consider the problem of diagnosing implementationnerrors in synchronous sequential circuits described by state tables. Thendiagnosis problem is formulated so as to provide the erroneouslynimplemented entries of the state table, which are useful for thenpurposes of debugging the synthesis procedure. The diagnosis procedurendeveloped is not limited to a specific error model and no bound is setnon error multiplicity. Experimental results are presented to show theneffectiveness of this procedure. The experiments indicate that statentables with certain properties make their implementations more amenablento diagnosis than others. These properties are used as guidelines fornsynthesis