As synthesis tools become more advanced and reliable, the entrynpoint for the designer in the design process is moving towards highernlevels of specification. Issues related to the specification of embeddednsystems are discussed. The authors compare VHDL with five othernspecification languages: HardwareC, SDL (Specification and DescriptionnLanguage), Statecharts, SpecCharts, and CSP (Communicating SequentialnProcesses). The capabilities of these languages with respect tonspecifying designs at the system-level are highlighted. The authorsnconclude by presenting a list of features which are desirable in anlanguage to be used for specifying systems
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