A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors

摘要

Chip Multiprocessors (CMPs) mainly base their performance gains on exploiting thread-level parallelism. Consequently, powerful mem ory systems Eire needed to support an increasing number of concur rent threads. Conventional CMP memory systems do not account for thread interference which can result in reduced overall system perfor mance. Therefore, conventional high bandwidth Miss Handling Archi tectures (MHAs) are not well suited to CMPs because they can create severe memory bus congestion. However, high miss bandwidth is desir able when sufficient bus bandwidth is available. This paper presents a novel, CMP-specific technique called the Adaptive Miss Handling Ar chitecture (AMHA). If the memory bus is congested, AMHA improves performance by dynamically reducing the maximum allowed number of concurrent L1 cache misses of a processor core if this creates a significant speedup for the other processors. Compared to a 16-wide conventional MHA, AMHA improves performance by 12% on average for one of the workload collections used in this work.