Address generators for linear processor array

摘要

In processor arrays, the memory subsystem represents a major cost and performance bottleneck. To optimize the system performance we use address generation unit which performs host-to-processor array address transformation in hardware. The aim of initial loading is to provide sequential access to data elements stored in processor array memory modules. The performance of the proposed solution are estimated by the speedup, which is defined as a ratio of the time needed to perform address transformation in software and in hardware. Proposed hardware implementation of address transformation gives a speedup of 2.3, with low hardware overhead. Most of address transformations are performed by cross-wiring