Dynamic and Noise Properties of PLL Circuits in GNSS Receivers

摘要

Different dynamic and noise characteristics of hardware-software systems of phase lock loops (PLL) within global navigation satellite systems (GNSS) receivers capable of operating under strong dynamic external effects have been considered in the present paper. Most operations in hardware-software systems are performed in processor at relatively low rate of time discretization, the signals of many satellite channels being successively processed by the processor. In the other, hardware part of the receiver, its own simultaneously operating channels correspond to each PLL system. A theoretical analysis of the considered PLL systems has been carried out by methods based on z-transformations. Then, these PLL systems were compared to each other with the help of simulation modeling in conditions of different dynamic impacts. In conclusion, some recommendations on selection of PLL systems of one or other type depending on GNSS receiver user's requirements have been given. These recommendations reflect the authors' previous experience in developing and designing commercial GNSS receivers.