Hierarchical test generation for VHDL behavioral models

摘要

In this method, the VHDL model to be tested is represented by itsnprocess model graph (PMG). Test sets for individual processes of thenmodel are precomputed and stored in the design library. The HierarchicalnBehavioral Test Generator (HBTG) algorithm accepts the PMG and thenprecomputed tests as inputs, from which it hierarchically constructs antest sequence that tests the functionality of the model. Such annautomatic test generation process relieves the modeler of thentime-consuming task of developing test-benches. The test sequencengenerated by HBTG is then used for simulation of the model. Experimentalnresults indicate that the tests generated exercise the model thoroughly