Architectural-level fault simulation using symbolic data

摘要

A fault simulation technique which uses architectural-levelninformation is proposed. This approach allows one to simulate stuck-atnfaults in specific modules within the context of the overall design.nGate-level descriptions of all modules are not required, so this methodncan be applied early in the design phase. At the architectural level,nthe behavioral simulation uses symbolic data to simultaneously processnthe fault effects for groups of faults in the module under simulation innorder to achieve speedup. The proposed techniques have been implemented,nand several circuits described at a high level have been simulatednsuccessfully using different test sets