首页> 外文会议>Symposium on Functional Nanostructured Materials Through Multiscale Assembly and Novel Patterning Techniques, Apr 2-5, 2002, San Francisco, California >MANIPULATION OF GERMANIUM NANOCRYSTALS IN A TRI-LAYER INSULATOR STRUCTURE OF A METAL-INSULATOR-SEMICONDUCTOR MEMORY DEVICE
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MANIPULATION OF GERMANIUM NANOCRYSTALS IN A TRI-LAYER INSULATOR STRUCTURE OF A METAL-INSULATOR-SEMICONDUCTOR MEMORY DEVICE

机译:金属绝缘体-半导电体存储器的三层绝缘体结构中锗纳米的操纵

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A metal-insulator-semiconductor (MIS) device that consists of germanium (Ge) nanocrystals embedded in a novel tri-layer insulator structure is proposed for memory applications [1]. The tri-layer structure comprises a thin (≈5nm) rapid thermal oxidation (RTO) silicon dioxide (SiO2) layer, a Ge+SiO_2 middle layer (6 - 20 nm) deposited by RF co-sputtering technique and a RF-sputtered silicon dioxide capping layer. High-resolution transmission electron microscopy (HRTEM) results show that Ge nanocrystals of sizes ranging from 6―20 nm were found after rapid thermal annealing of the tri-layer structure at 1000℃ for 300s. The electrical properties of these devices have been characterized using capacitance versus voltage (C-V) measurements. A significant hysteresis was observed in the C-V curves of these devices, indicating charge trapping in the composite insulator. Comparison with devices having similar tri-layer insulator structure, but with a pure sputtered oxide middle layer (i.e. minus the Ge nanocrystals), clearly indicated that the observed charge trapping is due to the presence of the Ge nanocrystals in the middle layer. The C-V measurements of devices without the capping SiO_2 layer exhibited no significant hysteresis as compared to the embedded Ge nanocrystal tri-layer devices. The HRTEM micrographs showed that the presence of the capping oxide is critical in the formation of nanocrystals for this structure. By varying the thickness of the middle layer, it was found that the maximum nanocrystal size correlates well with the middle layer thickness. This indicates that the nanocrystals are well confined by the RTO oxide layer and the capping oxide layer. In addition, Ge nanocrystals formed using a thinner middle layer were found to be relatively uniform in size and distribution. This structure, therefore, offers a possibility of fabricating memory devices with controllable Ge nanocrystals size.
机译:提出了一种由锗(Ge)纳米晶体嵌入新型三层绝缘体结构构成的金属绝缘体半导体(MIS)器件,用于存储应用[1]。该三层结构包括一个薄(≈5nm)的快速热氧化(RTO)二氧化硅(SiO2)层,一个通过RF共溅射技术沉积的Ge + SiO_2中间层(6-20 nm)和一个RF溅射硅二氧化碳覆盖层。高分辨率透射电子显微镜(HRTEM)的结果表明,在1000℃下对三层结构进行了300s的快速热退火后,发现了Ge纳米晶体,尺寸在6〜20nm之间。这些设备的电性能已通过电容与电压(C-V)的测量进行了表征。在这些器件的C-V曲线中观察到明显的磁滞现象,表明电荷在复合绝缘子中捕获。与具有类似三层绝缘体结构但具有纯溅射氧化物中间层(即,减去Ge纳米晶体)的器件的比较清楚地表明,观察到的电荷俘获是由于中间层中存在Ge纳米晶体。与嵌入式Ge纳米晶体三层器件相比,没有覆盖SiO_2层的器件的C-V测量没有显示出明显的滞后现象。 HRTEM显微照片显示,在该结构的纳米晶体形成过程中,封端氧化物的存在至关重要。通过改变中间层的厚度,发现最大纳米晶体尺寸与中间层厚度很好地相关。这表明纳米晶体被RTO氧化物层和覆盖氧化物层很好地限制。另外,发现使用较薄的中间层形成的Ge纳米晶体在尺寸和分布上相对均匀。因此,该结构提供了制造具有可控制的Ge纳米晶体尺寸的存储器件的可能性。

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