Efficient Memory Processors Design of Multiple Applications for Multiprocessor Architecture

摘要

Memory access latency and related operations scheduling are often the performances bottleneck in the parallel architecture design of Multiprocessor systems. In this paper we present a model of efficient memory operations, which is an on chip network transaction controller. Utilizing the controller model, we can replace the multiple transactions of memory accesses by the multilayer transactions, which use integrated high level transactions and local-memory computation to reduce the system's communication consumption. We implement a hierarchical memory processor cluster which is located near the memory and executes the memory operations. In our case studies, we applied the design to applications (parallel H.263 decoder) running on a FPGA MPSoC system and found that this transaction approach can improve performance by speedup ratio of 12.59.