Rapid acquisition adaptive zero-crossing DPLL

摘要

In the proposed work, an adaptive first order zero-crossing digital phase locked loop (AZC-DPLL) for rapid acquisition, reliable locking, and independent of input signal level is designed, simulated and subsequently implemented on an FPGA based reconfigurable system. The finite state machine controller of the AZC-DPLL senses any changes in input signal frequency and amplitude level, that may cause the loop to loose lock, and accordingly adjusts the loop gain to bring the loop in lock within a few samples. Through this adaptation process, the conflicting requirement of fast acquisition and reliable locking is achieved.