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Optimization of WAl_2O_3Cu(-Te) Material Stack for High-Performance Conductive-Bridging Memory Cells

机译:高性能导电桥接存储单元W Al_2O_3 Cu(-Te)材料堆栈的优化

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In this paper, we optimize the thermal stability of WAl_2O_3Cu and WAl_2O_3Cu-Te conductive-bridging cells for integration of 1-Transistor/1-Resistor (1T1R) memory elements. Thermal stability up to the back-end-of-line (BEOL) processing temperature of 400℃ is ensured by Cu-Te composition tuning and carbon alloying developments, while Cu in-diffusion processes during BEOL processing is limited through the engineering of thin Ti-, Ta-, and TiW-based metallic liners inserted at the Al_2O_3Cu(-Te) interface. The integrated 1T1R cells are demonstrated to operate in the nanosecond range using moderate voltages. Write endurance of >10~6 cycles is achieved using 10ns-short pulses while high voltage-disturb robustness is observed at lower voltages, resulting in excellent voltage-time characteristics of the cells. Finally, images of device filaments programmed in low- and high-resistance states are successfully obtained by means of conductive atomic-force-microscopy.
机译:在本文中,我们优化了WAl_2O_3Cu和WAl_2O_3Cu-Te导电桥接单元的热稳定性,以集成1-晶体管/ 1电阻(1T1R)存储元件。 Cu-Te组成调整和碳合金化发展确保了高达400℃的后端工艺温度的热稳定性,而BEOL加工过程中的Cu扩散过程受到薄Ti工程的限制。在Al_2O_3Cu(-Te)界面处插入基于-,Ta-和TiW的金属衬里。集成的1T1R电池在中等电压下可在纳秒范围内工作。使用10ns-短脉冲可实现> 10〜6个周期的写入耐力,而在较低电压下可观察到高电压干扰鲁棒性,从而使电池具有出色的电压-时间特性。最后,通过导电原子力显微镜成功地获得了以低阻和高阻状态编程的器件细丝的图像。

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