DC Power Bus Modeling in High-Speed Digital Designs Including Conductor and Dielectric Losses

摘要

Power bus design is a critical aspect in high-speed digital circuit designs. A circuit extraction approach based on a mixed-potential integral equation formulation is presented herein to model artitrary multilayer power bus structures including vertical discontinuities associated with surface mount (SMT) decouping capacitor interconnects. Both conductor and dielectric losses are incorporated, and included into the first principles formulation. The agreement of modeling and measurements demonstrates its effectiveness and utilization in power bus designs.