An FPGA-based 3D image processor with median and convolution filters for real-time applications

摘要

Median filtering and convolution operations constitute a significant portion of the preprocessing operations performed on digital images. Software implementations of 3D filters in standard general-purpose microprocessors do not match the speed requirements for real-time performance. Field Programmable Gate Arrays (FPGAs) allow implementing reconfigurable architectures that are sufficiently flexible to implement more than one operation in the existing hardware, yielding higher speed for real-time execution without compromising flexibility. We present an FPGA-based 3D image processor that allows real-time median and convolution filtering of 3D images. It includes a linear systolic array architecture for median filtering, which implements an algorithm based on bit-serial searching and majority voting, and a convolution pipeline, based on the fast embedded multiplier units in the FPGA and an optimized carry-save adders. The application of the above designs to 3D image preprocessing is described. A prototype implementation achieved voxel rates in excess of 220MHz.