This paper introduces a novel half-select resilient dual write wordline 8T (DW8T) SRAM with a sequential writing technique. The process scaling increases random variation that degrades SRAM operating margins, for which the proposed DW8T cell presents two features: half-VDD precharging write bitlines and dual write wordlines. The dual write wordlines are sequentially activated in a write cycle, and its combination with the half-VDD precharge suppresses the half-select problem. The DW8T SRAM with the sequential writing technique improve a half-select bit error rate by 71% at the disturb worst corner (FS, 125°C) and by 79% at a typical corner (CC, 25°C) over the conventional 8T, respectively. We implemented a 256-Kb DW8T SRAM and a half-VDD generator on a single chip in a 40-nm CMOS process. The measurement results of the seven samples show that the proposed DW8T SRAM achieves a VDDmin of 600 mV and improves the average VDDmin by 367 mV compared to the conventional 8T SRAM. The measured leakage power can be reduced by 25%.
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机译:本文介绍了一种采用顺序写入技术的新型半选择弹性双写入字线8T(DW8T)SRAM。工艺缩放增加了随机变化,从而降低了SRAM的工作裕度,为此,拟议的DW8T单元具有两个功能:半VDD预充电写位线和双写字线。双写字线在写周期中被顺序激活,并且其与半VDD预充电的组合可抑制半选择问题。与传统的8T相比,采用顺序写入技术的DW8T SRAM在干扰最严重的转折点(FS,125°C)时将半选择误码率提高了71%,在典型的转折点(CC,25°C)时将其提高了79%。 , 分别。我们在40nm CMOS工艺的单个芯片上实现了256-Kb DW8T SRAM和一个半VDD发生器。七个样本的测量结果表明,与传统的8T SRAM相比,所提出的DW8T SRAM的VDD min sub>为600 mV,平均VDD min sub>提高了367 mV。测得的泄漏功率可降低25%。
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