VIT University, Chennai, India,PESIT, #14, 1st Floor, Kamakya Main Road, BSK 3rd Stage, 5th Block, Bangalore 560085, India;
VIT University, Chennai, India;
PESIT, #14, 1st Floor, Kamakya Main Road, BSK 3rd Stage, 5th Block, Bangalore 560085, India;
PESIT, #14, 1st Floor, Kamakya Main Road, BSK 3rd Stage, 5th Block, Bangalore 560085, India;
Memory testing; Error correction codes; Cyclic codes; Matrix codes; Single versus multiple error correction;
机译:数字信号处理器中嵌入式存储器的不均等错误保护纠错码
机译:针对存储应用的双错误校正BCH代码中的有效错误检测
机译:单纠错-双相邻错误检测-三相邻错误检测-四相邻错误检测(秒-Taed-Teed Aed)代码的设计
机译:使用循环码嵌入存储器中的错误检测和校正
机译:无线传感器网络的错误检测和纠正代码的性能分析。
机译:针对具有嵌入式纠错的分子量子存储器
机译:在通信通道中使用汉明和循环码的错误检测和校正
机译:二元循环码的单一突发 - 纠错能力