Graduate School of Science and Technology, Keio University, 3-14-1 Hiyoshi, Kouhoku-ku, Yokohama, Kanagawa, Japan;
Graduate School of Science and Technology, Keio University, 3-14-1 Hiyoshi, Kouhoku-ku, Yokohama, Kanagawa, Japan;
Center for Computational Sciences, University of Tsukuba, 1-1-1, Tennodai Tsukuba-city, Ibaraki 305-8577, Japan;
Graduate School of Science and Technology, Keio University, 3-14-1 Hiyoshi, Kouhoku-ku, Yokohama, Kanagawa, Japan;
Center for Computational Sciences, University of Tsukuba, 1-1-1, Tennodai Tsukuba-city, Ibaraki 305-8577, Japan;
Interconnect for accelerators; GPU cluster; Accelerator computing; FPGA Interconnect; Task Level Pipeline;
机译:基于FPGA的层间流水线加速器,用于滤波器的重量平衡的稀疏完全卷积网络,具有重叠的百帘
机译:Virtex-4 FPGA中的有效硬件任务上下文切换
机译:Virtex-4 FPGA中的有效硬件任务上下文切换
机译:经由FPGA开关的多加速器任务水平流水线
机译:开发一项新颖的任务来研究在多个目标之间切换所涉及的认知和神经过程
机译:前期/下期失活会损害多个任务开关的记忆力但不会灵活选择熟悉的任务
机译:基于FPGA的层间流水线加速器,用于滤波器的重量平衡的稀疏完全卷积网络,具有重叠的平铺
机译:多个磁性开关模块同步到线性感应加法器加速器