EXECUTION ENVIRONMENT ON FPGA FOR SMART PC HETERO-CLUSTER

摘要

FPGAs tend to consume electric power in tens of milli-rnwatts, and the ability to parallelize the applications on FP-rnGas results in increased performance–to–power–efficiencyrnof FPGAs. FPGAs embedded into the computer clusterrnsystems have been proposed. Smart cluster systems whichrncontrol own power by themselves also have been proposed.rnFor smart cluster systems, it is important to reduce CO_2.rnTherefore, it is necessary to level power consumption in thernentire facility to use the electric power effectively. Then,rnsmart cluster systems are able to change the number ofrncompute nodes including FPGAs dynamically by the powerrnconsumption of entire facility to level the total power con-rnsumption of the cluster system and other electronic de-rnvices. In this paper, we will propose an execution environ-rnment on FPGA for smart PC hetero cluster called SPHC.rnThe FPGA calculation device is constructed by using thernASIP, Application Specific Instruction set Processor on thernFPGA. In preliminary evaluation, we compared a MAC (orrnF) processor and a normal processor. And we achievedrn60.7MFLOPS/W on FDTD.