Digital foreground calibration for SAR-ADCs with redundancy implementation

摘要

Successive-approximation A/D converter (SAR-ADC) compares input voltages with the voltages made by a DAC composed ofrncapacitor arrays. SAR-ADC has the advantages of low-power consumption and suitability to fine processes because it does not use OP-amps.rnHowever, the linearity of the ADC decreases when the fabricated binary weighted capacitors have mismatches. This study proposes to calibraternSAR-ADC using output digital codes. It is possible to improve accuracy by estimating the actual bit weight (changed due to capacitor mismatches),rnand by correcting the digital output using the actual bit weight. As a result, although a conventional SAR-ADC with capacitor mismatches has largernquantization error, whereas the proposed calibrated ADC has less quantization error which varies within about ±1/2LSB.