Digital logic simulation models and evolving technology

摘要

Digital logic simulators have traditionally served three functions for the designer; those are logic verification, design verification (detailed timing analysis), and fault analysis.

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Logic verification is well understood and accurate models have existed for this purpose for some time. Design verification has improved steadily over recent years and very accurate models exist for gate-level analysis. Fault analysis has progressed much more slowly, and most models currently used are quite limited.

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This paper details the evolution of models used in performing the three functions, and discusses current strategy; especially with respect to timing analysis and fault insertion. Current fault and timing models are discussed in light of current technology, with emphasis on the applicability of faults to such devices as emitter coupled logic and MOS-LSI. Adequate model detail for an integrated circuit based on knowledge of package terminal behavior is discussed, and certain problems encountered in adequate modeling of complex functions (such as multi-phase memories) are presented.