The transfer to a load from a sagged to a healthy source is affected by a number of factors which appear to be common to all applications and, where thyristors are used in the solid state switch, are largely independent of the algorithms used to regulate the high speed transfer. Morover, the time required to actually execute the load transfer is virtually independent of the rapidity with which a power quality event is detected. The total transfer time is the combination of detection time, and the effect of physical processes relted to the solid state devices used in the high speed switch. These physical processes depend on distribution system topology and the interaction between the load and its medium voltage supply network. The paper looks at detection times in a simple, yet commonly used, algorithm and illustrates the system features which act to further delay the transfer process. Static switches complete the majority of their transfers within 1/4 of a cycle, but users need to understand the basic processes which can drive the transfer. The paper illustrates those processes, and emphasises the need for rigourous testing to validate quoted performance.
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