Design complexity sometimes grows faster than EDA tools performances, and some innovation should be made on the design flow to guarantee the best possible validation in a reasonable time. This was the challenge we were facing for the final layout validation of a 3 billions transistors, multi cores chip designed for a 28nm process. The design backend validation requires multiple tools: the LVS to check connectivity, the DRC to check layout rules and the ERC to check any risk of power drop among the whole chip. While the 2 first tools are able to deal with huge designs by using hierarchical approaches, Electrical Rule Checking is much more complicated as the power routing is generally made flat at the top level of the chip. The classical ERC tools were not able to validate the power distribution at top level. The power distribution was made through a power grid using two metal layers and arrays of vias to connect each block at deeper metal layers. The chip is made of 256 processors and has a quite regular structure so that each module has it own power grid with the same pitch and every thing should be butting or properly connected at top level. It has then been decided to use a very efficient tool dedicated to geometrical verification of flat designs (typically a Mask Rule Checker) to check any interruption on power lines or missing vias in arrays. This paper will describe how this validation was performed as well as the performances obtained on a 28nm, 3 billions transistors design.
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