THE EVOLUTION OF CERAMIC PACKAGES FOR S/390 SERVERS

摘要

In the last decade of the 20th century a major redirection occurred to the chip technology of the S/390 servers. Specifically, the bipolar technology used for the chips comprising the Central Electronic Complex, e.g. CEC, was replaced by the CMOS technology. This resulted in one order of magnitude reduction of the volume of these servers as well as a similar reduction in the power consumption of the CEC electronics. However, such volumetric reduction could not have been achieved without the ceramic multi-chip Module that housed the chip set comprising the CEC. Indeed this MCM technology was one of the constants through this transition period for the S/390 servers because of its direct chip attach capability, excellent electrical properties, and almost unlimited wireability. In this paper we will present the evolution of this packaging technology and its key attributes that permitted the doubling of the number of CPUs within four system generations ( e.g. five years) along with the required increase by 8 times of the size of the shared L2 cache and the intra chip interconnect bandwidth. These enhancements in system technology made possible the improvement of the S/390 system performance by one order of magnitude. The wiring strategies employed to achieve the required interconnection bandwidth will be highlighted along with the decoupling approaches used to contain the switching noise in these modules. In addition, the capabilities and cost performance of this packaging technology for various memory hierarchies will be presented.