Lithographic performance at sub-300-nm design rules using a high-NAI-line stepper with optimized NA and (sigma) in conjunction with advanced PSMtechnology,

摘要

Abstract: There is growing consensus that 350 nm design rules will be accomplished using i-line lithography. Recent developments in i-line lithography have pushed NA and field size to acceptable levels for 64 MB DRAM manufacturing. Simpler PSM technologies may be used to augment performance in first generation 64 MB DRAM manufacturing. Depending on the topography requirements, it may be necessary to have more process latitude at critical line/space layers. I-line lithography, with conventional binary intensity masks (BIM) should provide adequate process latitude at 400 nm design rules. Incremental improvements in process latitude at feature sizes around this design rule can be obtained using attenuated phase PSM technology. This paper presents data on the implementation of BIM and various PSM technologies in conjunction with a variable NA, variable $sigma i-line stepper. Optimization of NA and $sigma have been performed using the various mask technologies to maximize process latitude at features sizes from 450 nm down to below 300 nm. Ultimately, a path is provided to achieve adequate lithographic performance for both first and second generation 64 MB DRAM manufacturing. !4