Lithographic performance at sub-300-nm design rules using a high-NA I-line stepper with optimized NA and (sigma) in conjunction with advanced PSM technology

摘要

Abstract: There is growing consensus that 350 nm design ruleswill be accomplished using i-line lithography. Recentdevelopments in i-line lithography have pushed NA andfield size to acceptable levels for 64 MB DRAMmanufacturing. Simpler PSM technologies may be used toaugment performance in first generation 64 MB DRAMmanufacturing. Depending on the topographyrequirements, it may be necessary to have more processlatitude at critical line/space layers. I-linelithography, with conventional binary intensity masks(BIM) should provide adequate process latitude at 400nm design rules. Incremental improvements in processlatitude at feature sizes around this design rule canbe obtained using attenuated phase PSM technology. Thispaper presents data on the implementation of BIM andvarious PSM technologies in conjunction with a variableNA, variable $sigma i-line stepper. Optimization of NAand $sigma have been performed using the various masktechnologies to maximize process latitude at featuressizes from 450 nm down to below 300 nm. Ultimately, apath is provided to achieve adequate lithographicperformance for both first and second generation 64 MBDRAM manufacturing. !4